Signals in digital circuits typically have one driver pin and one or more load pins. A logic transition on a signal during circuit operation commences at the driver of the signal and is received at a load pin at some point later in time. The propagation delay from a signal driver to the load pin depends on the routing topology, capacitance, and buffering in the signal path. The propagation delay from the signal driver to a load may vary based upon a selected path. This important signal transmission property, called the signal “skew,” is the difference in propagation delay of a signal routed to a load in different paths. Similarly, “clock skew” refers to skew on the clock network. Clock skew can have a considerable impact on the performance of sequential logic circuits, and can often reduce the performance of sequential circuits by reducing the permissible propagation time for combinational paths.
In synchronous logic, a pipeline stage with the longest data path delay limits the maximum frequency (Fmax) of the entire design, even if the previous or next pipeline stages are very fast. Conventionally, clock skew is added by introducing a programmable delay element before the clock pin of the target register. The area required for implementing the delay grows linearly with the number of registers and a maximum delay, which significantly increases the cost of an integrated circuit device transmitting data.